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dual 8 - /10 - /12 - bit, high bandwidth, multiplying dacs with parallel interface ad5428/ad5440/ad5447 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. spec ifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 200 4C 2011 analog devices, inc. all rights reserved. features 10 mhz multiplying bandwidth inl of 0.25 lsb @ 8 bit s 20- lead and 24 - lead tssop packages 2.5 v to 5.5 v supply operation 10 v reference input 21.3 msps update rate extended temperature range : ?40c to + 125c 4- quadrant multiplication power - on res et 0.5 a typical current consumption guaranteed monotonic readback function ad7528 upgrade (ad5428) ad7547 upgrade (ad5447) applications portable battery - powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5428/ad5440/ad5447 1 as a result of being manufacture d on a cmos submicron process, they offer excellent 4 - quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 mhz. are cmos, 8 - , 10 - , and 12 - bit, dual - channel, curr ent output digital - to - analog converters (dacs), respectively. these devices operate from a 2.5 v to 5.5 v power supply, making them suited to battery - powered and other applications. the dacs use data readback, allowing the user to read the contents of the dac register via the db pins. on power - up, the internal register and latches are filled with 0s, and the dac outputs are at zero scale. the applied external reference input voltage (v ref ) determines the full - scale output current. an integrated feedback resistor (r fb ) provides temperature tracking and full - scale voltage output when combined with an external i - to - v precision amplifier. the ad5428 is available in a small 20 - lead tssop package, and the ad5440/ad5447 dacs are available in small 24 - lead tssop packages. 1 u.s. patent number 5,689,257. functional block diagram 04462-001 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v ref b r fb a r fb b r r figure 1. a d5428/ad5440/ad5447
ad5428/ad5440/ad5447 rev. b | page 2 of 32 table of contents specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ........................................... 10 terminology .................................................................................... 15 general description ....................................................................... 16 dac section ................................................................................ 16 circuit operation ....................................................................... 16 single - supply applications ....................................................... 19 adding gain ................................................................................ 19 divider or programmable gain element ................................ 20 reference selection .................................................................... 20 amplifier selection .................................................................... 20 parallel interface ......................................................................... 22 microprocessor in terfacing ....................................................... 22 pcb layout and power supply decoupling ........................... 23 evaluation board for the dacs ................................................ 23 power supplies for the evaluation board ................................ 23 bill of materials ............................................................................... 27 overview of ad54xx devices ....................................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 3/ 11 rev. a to rev. b changes to evaluation bo ard for the ad5447 section ............ 23 changes to figure 47 caption ....................................................... 24 changes to figure 49 ...................................................................... 25 change to u1 description in table 12 ......................................... 27 change to ordering guide ............................................................ 29 7 /05 rev. 0 to rev. a changed pin dac a/b to dac a /b ............................... universal changes to features l ist .................................................................. 1 changes to specifications ................................................................ 3 changes to timing characteristics ................................................ 5 change to figure 2 ........................................................................... 5 change to absolute maximum ratings section ........................... 6 change to figure 13, figure 14, and figure 18 ........................... 11 change to figure 32 through figure 34 ..................................... 14 changes to general description section .................................... 16 changes to figure 37 ...................................................................... 16 changes to single - supply applications section ......................... 19 changes to figure 40 through figure 42 .................................... 19 changes to divider or programmable gain element section .... 20 changes to figure 43 ...................................................................... 20 changes to table 9 through table 11 ......................................... 21 changes to microprocessor interfacing section ........................ 22 added figure 44 through figure 46 ........................................... 22 added 8xc51 - to - ad5428/ad5440/ad5447 interface section ........................................................................ 22 added adsp - bf5xx - to - ad5428/ad5440/ad5447 interface section ........................................................................ 22 changes to power supplies for the evaluation b oard section .... 23 changes to table 13 ....................................................................... 28 updated outline dimensions ....................................................... 29 changes to ordering guide .......................................................... 29 7/04 revision 0: initial version
ad5428/ad5440/ad5447 rev. b | page 3 o f 32 specifications 1 v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. tempe rature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance is measured with op177, and ac performance is measured with ad8038, unless otherwise noted. table 1 . parameter mi n typ max unit conditions static performance ad5428 resolution 8 bits relative accuracy 0. 2 5 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5440 resolution 10 bits relative accuracy 0 .5 lsb differential nonlinearity 1 lsb guaranteed m onotonic ad5447 resolution 12 bits relative accuracy 1 lsb differential nonlinearity C 1/+2 lsb guaranteed m onotonic gain error 25 m v gain error temp erature c oefficient 5 ppm fsr/c output leakage current 5 na data = 0x 0000, t a = 25 c 15 na data = 0x0000 reference input reference input range 10 v v ref a, v ref b input resistance 8 10 13 k? input resistance tc = C 50 ppm/c v ref a- to -v ref b input resistance mism atch 1.6 2.5 % typ = 25c, max = 125c input capacitance code 0 3.5 pf code 4095 3.5 pf digital inputs/output input high voltage, v ih 1.7 v v dd = 3.6 v to 5.5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5.5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5.5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance reference - multiplying bw 10 mhz v ref = 3.5 v p-p , dac loaded all 1s output voltage settling time r load = 100 ? , c load = 15 pf, v ref = 10 v dac latch alternately loaded with 0s and 1s measure d to 1 mv of fs 80 120 ns measured to 4 mv of fs 35 70 ns measured to 16 mv of fs 30 60 ns digital delay 20 40 ns interface delay time 10% to 90% settling time 15 30 ns rise and fall time s , v ref = 10 v, r load = 100 ? digital -to - analog g litch impulse 3 nv - s ec 1 lsb change around major carry, v ref = 0 v
ad5428/ad5440/ad5447 rev. b | page 4 of 32 parameter mi n typ max unit conditions multiplying feedthrough error dac latches loaded with all 0 s, v ref = 3.5 v 70 db 1 mhz 48 db 10 mhz output capacitance 12 17 pf dac latches loaded with all 0s 25 30 pf dac latches loaded with all 1s digital feedthrough 1 nv - sec feedthrough to dac output with cs high and alternate loading of all 0s and all 1s output noise spectral density 25 nv/ hz @ 1 khz analog thd 81 db v ref = 3.5 v p - p, all 1s loaded, f = 100 khz digital thd clock = 10 mhz, v ref = 3.5 v 100 khz f out 61 db 50 khz f out 66 db sfdr performance (wide b and) ad5447, 65 k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) ad5447, 65 k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50k hz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50 khz f out 80 db intermodulation distortion ad5447, 65 k codes, v ref = 3.5 v f 1 = 40 khz, f 2 = 50 k hz 72 db clock = 10 mhz f 1 = 40 khz, f 2 = 50 khz 65 db clock = 25 mhz power requirements power supply range 2.5 5.5 v i dd 0 .7 a t a = 25c, logic inputs = 0 v or v dd 0.5 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd power supply sensitivity 0.001 %/% ?v dd = 5% 1 guaranteed by design, not subject to production test.
ad5428/ad5440/ad5447 rev. b | page 5 o f 32 timing characteristi cs all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range fo r y version: ? 40c to +125c. a ll specifications t min to t max , unless otherwise noted . table 2 . parameter 1 limit at t min , t max unit conditions/comments write mode t 1 0 ns min r/ w to cs setup time t 2 0 ns min r/ w to cs hold time t 3 10 ns min cs low time t 4 10 ns min address setup time t 5 0 ns min address hold time t 6 6 ns min data setup time t 7 0 ns min data hold time t 8 5 ns min r/ w high to cs low t 9 7 ns min cs min high time data readback mode t 10 0 ns typ address setup time t 11 0 ns typ address hold time t 12 5 ns typ d ata access time 25 ns max t 13 5 ns typ bus relinquish time 10 ns max update rate 21.3 msps consists of cs min high time, cs low time, and output voltage settling time 1 guaranteed by design and characterization, not subject to production test. 04462-002 data valid data valid data daca/dacb cs r/w t 1 t 3 t 4 t 10 t 5 t 8 t 7 t 11 t 9 t 2 t 8 t 2 t 12 t 13 figure 2 . timing diagram 04462-003 to output pin v oh (min) + v ol (max) 200 a i oh 200 a i ol 2 c l 50pf figure 3 . load circuit for data output timing specifications
ad5428/ad5440/ad5447 rev. b | page 6 of 32 absolute maximum rat ings t ransient currents of up to 100 ma do not cause scr latch - up. t a = 25 c, unless otherwise noted. table 3 . parameter rating v dd to gnd C 0.3 v to +7 v v ref a, v ref b, r fb a, r fb b to d gnd C 12 v to +12 v i out 1, i out 2 to d gnd C 0.3 v to +7 v logic inputs and output 1 C 0.3 v to v dd + 0.3 v operating temperature range automotive (y version) C 40c to +125c storage temperature range C 65c to +150c junction temperature 150c 20- lead tssop ja thermal impedance 143c/w 24- lead tssop ja thermal impedance 128c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at dbx, cs , and r/ w are clamped by internal diodes. stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution esd (electrostatic discha rge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5428/ad5440/ad5447 rev. b | page 7 o f 32 pin configurations and function descript ions 04462-004 r/w cs 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db7 dac a/b dgnd agnd r fb b v ref b v dd db0 (lsb) db4 db5 db6 db3 db2 db1 i out b ad5428 top view (not to scale) figure 4. pin configuration 20 - lead tssop (ru - 20) table 4 . ad5428 pin function description s pin no. mnemonic description 1 agnd dac ground p in. t his pin should typically be tied to the analog ground of the system, but can be biased to a chieve single - supply operation. 2, 20 i out a, i out b dac current outputs. 3, 19 r fb a , r fb b dac f eedback r esistor p in s . these pins e stablish voltage output for the dac by connecting to an external amplifier output. 4, 18 v ref a , v ref b dac r eference v oltage i nput t erminal s . 5 dgnd digital ground p in. 6 dac a /b selects dac a or dac b. low selects dac a; high selects dac b. 7 to 14 db7 to db0 parallel data bits 7 t hrough 0. 15 cs chip select input. a ctive l ow. used in conjunction with r/ w to load parallel data to the input latch or to read data from the dac register. 16 r/ w read/write. when low, used in conjunction with cs to load parallel data. when high, used in conjunction with cs to read back contents of the dac r egister. 17 v dd positive p ower s upply i nput. t his part can be operated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad5447 rev. b | page 8 of 32 04462-005 r/w cs 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db9 dac a/b dgnd agnd r fb b v ref b v dd nc db8 db7 db4 db5 db6 nc db0 (lsb) db3 db2 db1 i out b ad5440 top view (not to scale) nc = no connect figure 5. pin configuration 24-lead tssop (ru-24) table 5. ad5440 pin function descriptions pin no. mnemonic function 1 agnd dac ground pin. this pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 24 i out a, i out b dac current outputs. 3, 23 r fb a, r fb b dac feedback resistor pins. establ ish voltage output for the dac by co nnecting to an external amplifier output. 4, 22 v ref a, v ref b dac reference voltage input terminals. 5 dgnd digital ground pin. 6 dac a /b selects dac a or dac b. low selects dac a; high selects dac b. 7 to16 db9 to db0 parallel data bits 9 through 0. 19 cs chip select input. active low. used in conjunction with r/w to load parallel data to the input latch or to read data from the dac register. 20 r/w read/write. when low, used in conjunction with cs to load parallel data. when hi gh, used in conjunction with cs to read back contents of the dac register. 21 v dd positive power supply input. this part can be operated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad5447 rev. b | page 9 o f 32 04462-006 r/w cs 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db11 dac a/b dgnd agnd r fb b v ref b v dd db0 (lsb) db10 db9 db6 db7 db8 db1 db2 db5 db4 db3 i out b ad5447 top view (not to scale) figure 6 . pin configuration 24- lead tssop (ru - 24) table 6 . ad5447 pin function description s pin no. mnemonic description 1 agnd dac ground p in. t his pin should typically be tied to the analog ground of the system, but can be biased to achieve single - supply operation. 2, 24 i out a, i out b dac current outputs. 3, 23 r fb a , r fb b dac f eedback r esistor p in s . e stablish voltage output for the dac by connecting to an external amplifier output. 4, 22 v ref a , v ref b dac reference voltage input terminals. 5 dgnd digital ground p in. 6 d ac a /b selects dac a or dac b. low selects dac a ; high selects dac b. 7 to 18 db11 to db0 parallel data bits 11 t hrough 0. 19 cs chip select input. active l ow. used in conjunction with r/ w t o load parallel data to the input latch or to read data from the dac register. when cs and r/ w are held low, the latches are transparent . a ny changes on the data lines are reflected in the relevant dac output. 20 r/ w read/write. when low, used in conjunction with cs to load parallel data. when high, used in conjunction with cs to read back the contents of the dac r egister. when cs and r/ w are held low, the latches are transparent . a ny changes on the data lines are reflected in the relevant dac output. 21 v dd positive p ower s upply input. this part ca n be operated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad5447 rev. b | page 10 of 32 typical performance characteris tics ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 inl (lsb) 0.10 0.15 0.20 04462-007 0 50 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v figure 7 . inl vs. code (8 - bit dac) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 inl (lsb) 04462-008 0 200 400 600 800 1000 code t a = 25c v ref = 10v v dd = 5v figure 8 . inl vs. code (10 - bit dac) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04462-009 t a = 25c v ref = 10v v dd = 5v figure 9 . inl vs. code (12 - bit dac) ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 dnl (lsb) 0.10 0.15 0.20 04462-010 0 50 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v figure 10 . dnl vs. code (8 -b it dac) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) 04462-011 0 200 400 600 800 1000 code t a = 25c v ref = 10v v dd = 5v figure 11 . dnl vs. code (10 - bit dac) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04462-012 t a = 25c v ref = 10v v dd = 5v figure 12 . dnl vs. code (12 - bit dac)
ad5428/ad5440/ad5447 rev. b | page 11 o f 32 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl (lsb) 65 3 4 2 7 8 9 10 reference voltage 04462-013 max inl min inl t a = 25c v dd = 5v figure 13 . inl vs. reference voltage ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (lsb) 65 3 4 2 7 8 9 10 reference voltage 04462-014 min dnl t a = 25c v dd = 5v figure 14 . dnl vs. reference voltage ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 error (mv) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04462-015 v dd = 5v v dd = 2.5v v ref = 10v figure 15 . gain error vs. temperature input voltage (v) current (ma) 8 5 0 5.0 7 6 3 1 4 2 4.54.03.5 3.02.52.01.5 1.00.50 v dd = 5v v dd = 3v v dd = 2.5v 04462-022 t a = 25c figure 16 . supply current vs. logic input voltage 0 0.2 0.4 0.6 0.8 1.0 i out 1 leakage (na) 1.2 1.4 1.6 4020 ?20 0 ?40 60 80 100 120 temperature (c) 04462-023 i out 1 v dd = 5v i out 1 v dd = 3v figure 17 . i out 1 leakage current vs. temperature 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current (a) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04462-024 v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s figure 18 . supply current vs. temperature
ad5428/ad5440/ad5447 rev. b | page 12 of 32 0 2 4 6 8 10 12 14 i dd (ma) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04462-025 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v figure 19 . supply current vs. update rate ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) t a = 25c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf amp = ad8038 all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04462-026 10 figure 20 . reference multiplying bandwidth vs. frequency and code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 gain (db) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04462-027 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf amp = ad8038 figure 21 . reference multiplying bandwidth all 1 s loaded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v gain (db) 04462-028 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf figure 22 . reference multiplying bandwidth vs. frequency and compensation capacitor ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04462-041 t a = 25c v ref = 0v amp = ad8038 c comp = 1.8pf 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v figure 23 . midscale transition, v ref = 0 v output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04462-042 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v amp = ad8038 c comp = 1.8pf figure 24 . midscale transition, v ref = 3.5 v
ad5428/ad5440/ad5447 rev. b | page 13 o f 32 ?120 ?100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (db) 04462-043 10 figure 25 . power supply rejection ratio vs. frequency ?90 ?85 ?80 ?75 ?70 ?65 ?60 thd + n (db) 100 1k 1 10 10k 100k 1m frequency (hz) 04462-044 t a = 25c v dd = 3v v ref = 3.5v p-p figure 26 . thd + noise vs. frequency 0 20 40 60 80 100 sfdr (db) 0 20 40 60 80 100 120 140 160 180 200 f out (khz) 04462-045 t a = 25c v ref = 3.5v amp = ad8038 mclk = 1mhz mclk = 200khz mclk = 0.5mhz figure 27 . wideband sfdr vs. f out frequency 0 10 20 30 40 50 60 70 80 90 sfdr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04462-046 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v amp = ad8038 figure 28 . wideband sfdr vs. f out frequency 04462-047 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25c v dd = 5v amp = ad8038 65k codes 2 4 6 8 10 12 figure 29 . wideband sfdr, f out = 100 khz, clock = 25 mhz ? 04462048 ?100 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?90 figure 30 . wideband sfdr, f out = 500 khz, clock = 10 mhz
ad5428/ad5440/ad5447 rev. b | page 14 of 32 04462-049 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25c v dd = 5v amp = ad8038 65k codes figure 31 . wideband sfdr, f out = 50 khz, clock = 10 mhz 04462-050 frequency (khz) ? t a = 25 c v dd = 3v amp = ad8038 65k codes ?100 ?70 ?50 ?30 ?10 sfdr (db) 250 750 300 350 400 650 700 ?80 ?60 ?40 ?20 0 ?90 450 500 550 600 figure 32 . narrow - band sfdr , f out = 500 khz, clock = 25 mhz 04462-051 ?120 ?60 ?20 sfdr (db) 50 150 frequency (khz) 60 70 80 130 140 ?80 ?40 0 20 ?100 90 100 110 120 ? t a = 25 c v dd = 3v amp = ad8038 65k codes figure 33 . narrow - band sfdr, f out = 100 khz, clock = 25 mhz 04462-052 frequency (khz) ?100 ?70 ?50 ?30 ?10 imd (db) 70 120 75 80 85 115 ?80 ?60 ?40 ?20 0 ?90 90 100 105 110 ? t a = 25 c v dd = 3v amp = ad8038 65k codes 95 figure 34 . narrow - band imd, f out = 90 khz, 100 khz, clock = 10 mhz 04462-53 ?100 ?40 ?20 imd (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 ? t a = 25c v dd = 5v amp = ad8038 65k codes figure 35 . wideband imd, f out = 90 khz, 100 khz, clock = 25 mhz 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04462-054 0 50 100 150 200 250 300 output noise (nv/ hz) midscale loaded to dac figure 36 . output nois e spectral density
ad5428/ad5440/ad5447 rev. b | page 15 of 32 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is typically expressed in lsbs or as a percentage of the full-scale reading. differential nonlinearity the difference in the measured change and the ideal 1 lsb change between two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error (full-scale error) a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref C 1 lsb. the gain error of the dacs is adjustable to zero with an external resistance. output leakage current the current that flows into the dac ladder switches when they are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows into the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time the amount of time for the output to settle to a specified level for a full-scale input change. for these devices, it is specified with a 100 resistor to ground. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-sec or nv-sec, depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs is capacitively coupled through the device and produces noise on the i out pins and, subsequently, on the following circuitry. this noise is digital feedthrough. multiplying feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower-order harmonics are included, such as second to fifth harmonics. 1 54 32 v vvvv thd 2222 log20 ??? ? digital intermodulation distortion second-order intermodulation distortion (imd) measurements are the relative magnitude of the fa and fb tones digitally generated by the dac and the second-order products at 2fa ? fb and 2fb ? fa. spurious-free dynamic range (sfdr) sfdr is the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. sfdr is the measure of difference in amplitude between the fundamental and the largest harmonic or nonharmonic spur from dc to full nyquist bandwidth (half the dac sampling rate, or fs/2). narrow-band sfdr is a measure of sfdr over an arbitrary window size, in this case 50%, of the fundamental. digital sfdr is a measure of the usable dynamic range of the dac when the signal is a digitally generated sine wave.
ad5428/ad5440/ad5447 rev. b | page 16 of 32 general description dac section the ad5428 / ad5440 / ad5447 are cmos 8 - , 10 - , and 12 - bit, dual - channel , current output dacs consisting of a standard inverting r - 2r ladder configuration. figure 37 shows a simplified diagram for a single channel of the 8 -b it ad5428 . the feedback resistor r fb a has a value of r. the value of r is typically 10 k? ( with a minimum of 8 k ? and a maximum of 12 k? ). if i out 1 and agnd are kept at the same potential, a constant current flows in to each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref a is always constant and nominally of value r. the dac output (i out ) is code - depende nt, producing various resistances and capacitances. when choosing an e xternal amplifier , take into account the variation in impedance generated by the dac on the amplifier s inverting input node. 04462-029 v ref dac data latches and drivers r fb a i out a agnd r r r r 2r 2r 2r 2r 2r s1 s2 s3 s8 figure 37 . simplified ladder acce ss is provided to the v ref , r fb , and i out terminals of dac a and dac b , making the device s extremely versatile and allowing them to be configured in sev eral operating modes , such as unipolar output mode , 4 - quadrant multiplicati on bipolar mode , or single-su pply mode . note that a matching switch is used in series with the internal r fb a feedback resistor. if users attempt to measure r fb a , power must be applied to v dd to achieve continuity. circuit operation unipolar mode using a single op amp, these devices can easily be configur ed to provide 2- quadrant multiplying operation or a unipolar output voltage swing , as shown in figure 38 . when an output amplifier is connected in unipolar mode, the output voltage is given by n ref out dvv 2/ ?= w here : d is the f ractional representation of the digital word loaded to the dac . d = 0 to 255 (8 -b it ad5428) = 0 to 1023 (10 -b it ad5440) = 0 to 4095 (12 -b it ad5447) n is the resolution of the dac. note that the output voltage polarity is opposite to th e v ref polarity for dc reference voltages. these dacs are designed to operate with either negative or positive reference voltages. the v dd power pin is only used by the internal digital logic to drive the on and off states of the dac switches. these dacs are also designed to accommodate ac reference input signals in the range of C 10 v to +10 v. with a fixed 10 v reference, the circuit in figure 38 give s a unipolar 0 v to C 10 v output voltage swing. when v in is an ac signal, the circuit performs 2- quadrant multiplication. table 7 shows the relationship between digital code and the expected output voltage for unipolar operation using the 8 - bit ad5428 . table 7. unipolar code digital input analog output (v) 1111 1111 Cv ref (255/256) 1000 0000 Cv ref (128/256) = Cv ref /2 0000 0001 Cv ref (1/256) 0000 0000 Cv ref (0/256) = 0
ad5428/ad5440/ad5447 rev. b | page 17 o f 32 04462-030 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch agnd 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v in a (10v) v ref b r fb a r fb b r r v out a r1 1 v in b (10v) r3 1 r2 1 c1 2 agnd v out b r4 1 c2 2 1 r1, r2 and r3, r4 used only if gain adjustment is required. 2 c1, c2 phase compensation (1pf to 2pf) is required when using high speed amplifiers to prevent ringing or oscillation. figure 38 . unipolar operation
ad5428/ad5440/ad5447 rev. b | page 18 of 32 bipolar operation i n some applications, it may be necessary to generate full 4 - quad - rant multiplying operation or a bipolar output swing. this can easily be accomplished by using another external amplifier and some external resistors, as shown in figure 39 . in this circuit, the second amplifier, a2, provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in full 4- quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code 0 (v out = ?v ref ) to mid scale (v out = 0 v) to full scale (v out = +v ref ). when connected in bipolar mode, the output voltage is given by ( ) ref n ref out v dvv ?= ? 1 2/ where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 255 (ad5428) = 0 to 1023 (ad5440) = 0 to 4095 (ad5447) n is the number of bits. when v in is an ac signal, the circuit performs 4 - quadran t multiplication. table 8 shows the relationship between digital code and the expected output voltage for bipolar operation using the 8 - bit ad5428. table 8 . bipolar code digital input analo g output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 Cv ref (127/128) 0000 0000 Cv ref (128/128) stability in the i - to - v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible, an d proper pcb layout techniques must be us ed. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this pa rasitic capacitance introduces a pole into the open - loop response, which can cause ringing or instability in the closed - loop applications circuit. an optional compensation capacitor, c1, can be added in parallel with r fb a for stability, as shown in figure 38 and figure 39 . to o small a value of c1 can produce ringing at the output, whereas too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate f or the compensation. 04462-031 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch agnd 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v in a (10v) v ref b r fb a r fb b r r r2 1 v out a r1 1 v in b (10v) r3 1 r6 2 20k? r5 20k? r8 20k? r11 5k? r12 5k? r7 2 10k? r9 2 10k? r10 2 20k? c1 3 agnd agnd agnd v out b r4 1 c2 3 a1 a3 a2 a4 1 r1, r2 and r3, r4 used only if gain adjustment is required. adjust r1 for v out a = 0v with code 10000000 in dac a latch. adjust r3 for v out b = 0v with code 10000000 in dac b latch. 2 matching and tracking is essential for resistor pairs r6, r7 and r9, r10. 3 c1, c2 phase compensation (1pf to 2pf) may be required if a1/a3 is a high speed amplifier. figure 39 . bipolar operation (4 - quadrant multiplication)
ad5428/ad5440/ad5447 rev. b | page 19 o f 32 single - supply applications voltage- switching mode figure 4 0 shows the dacs operating in voltage - switching mode. the reference voltage, v in , is appl ied to the i out a pin , and the output voltage is available at the v ref a terminal. in this configuration, a positive reference voltage results in a positi ve output voltage , making single - supply operation possible. the output from the dac is voltage at consta nt impedance (the dac ladder resistance) . therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees constant input impedance, but one that varies with code. therefore , the voltage input should be driven from a low i mpedance source. note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source - drain drive voltage. as a result, their on resistance differs and degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 v , or an internal diode turns on, causing the device to exceed the maximum ratings . in this type of application, the full range of multiplying capability of the dac is lost. 04462-033 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v dd v in v ref a v dd r fb a gnd v out i out a agnd r1 r2 figure 40 . single - supply voltage- switching mod e positive output voltage t he output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the outpu t inversion through an inverting amplifier because of the resistor s tolerance errors. to generate a negative reference, the reference can be level - shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and C2.5 v, respectively , as shown in figure 41. 04462-034 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v dd = 5v v dd c1 v in v ref a r fb a 8-/10-/12-bit dac adr03 gnd gnd v out v out = 0v to 2.5v i out a agnd +5v ?5v ?2.5v figure 41 . positive voltage o utput with m inimum components adding gain in applications where the output voltage must be greater than v in , gain can be added with an additional external amplifier , or it can be achieved in a single stage. c onsider the effect of temper - ature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor cause s mis matches in the t emperature coefficients , resulting in larger gain temper - ature coefficient errors. instead, the circuit in figure 42 shows the recommended method for increasing the gain of the circuit. r1, r2 , and r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required. 04462-035 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v dd v dd c1 v in v ref a r fb a r1 r3 r2 8-/10-/12-bit dac gnd v out i out a agnd r2 + r3 r2 gain = r 1 = r2r3 r2 + r3 figure 42 . increasing gain of current output dac
ad5428/ad5440/ad5447 rev. b | page 20 of 32 divider or programma ble gain element current -s teering dacs are very flexible and lend themselves to many applications. if this type of dac is connected as the feedback element of an op amp and r fb a is used as the input resistor, as shown in figure 43 , the output voltage is inversely proportional to the digital input fraction , d. for d = 1 ? 2 ?n , the output voltage is ( ) n in in out vdvv ? ??=?= 21// v out v dd gnd v in agnd i out a r fb a v dd v ref a notes 1. additional pins omitted for clarity. 04462-040 figure 43 . current - steering dac used as a divider or programmable gain element as d is reduced, the output voltage increases. for small values of the digital fraction d, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. for example, an 8 - bit dac dr iven with the binary code 0x10 (0001 0000) that is, 16 decimal in the circuit of figure 43 should cause the output voltage to be 16 times v in . however, if the dac has a linearity specification of 0.5 lsb, d can h ave a weight in the range of 15.5/256 to 16.5/256 so that the possible output voltage is in the range of 15.5 v in to 16.5 v in an error of 3% , even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in d ivider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. because only a fraction , d, of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage change s as f ollows : output error voltage due to dac leakage ( ) drleakage / = where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k ?, and a gain ( that is , 1 /d) of 16 , the error voltage is 1.6 m v. reference selection when selecting a r eference for use with the ad54 xx series of current output dacs, pay attention to the reference s output voltage temperature coefficient specification. this para meter not only affects the full - scale error, but can also affect the linearit y (inl and dnl) performance. the reference temperature coefficient should be consistent with the system accuracy specifications. for example, an 8 - bit system required to hold its overall specification to within 1 lsb over the temperature range 0 to 50 c d ictates that the maximum system drift with temp - erature should be less than 78 ppm/ c. a 12 -b it system with the same temperature range to overall specification within 2 lsbs requires a maximum drift of 10 ppm/ c. c hoosing a precision reference with low out put temperature coefficient minimizes this error source . table 9 lists some references available from analog devices that are suitable for use with th ese current output dacs. amplifier selection the primary requir ement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac, t he input offset voltage of an op amp is multiplied by the variable gain of the circu it. a change in the noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which , if large enough , could cause the dac to be non monotonic. t he input offset voltage should be <1/4 lsb to ensure monotonic behavior when stepping through codes. the input bias cur r ent of an op amp al so generates an offset at the voltage output as a result of the bias current f lowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12 -b it applications. c ommon - mode rejection of the op amp i s important in voltage - switching circuits, because it produces a code - dependent error at the voltage output of the circuit. most op amps have adequate common - mode rejection for use at 8- , 10 - , and 12 -b it resolution. provided that the dac switches are drive n from true wideband , low impedance sources (v in and agnd) , they settle quickly. consequently , the slew rate and settling time of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configurat ion, minimize capacitance at the v ref node ( the voltage output node in this application) of the dac by using low input capacitance buffer amplifiers and careful board design. most single - supply circuits include ground as part of the analog signal range, wh ich in turns requires an amplif i er that can handle rail - to - rail signals. analog devices offers a wide variety of single - supply amplifiers (see table 10 and table 11 ).
ad5428/ad5440/ad5447 rev. b | page 21 o f 32 tab le 9 . suitable adi precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p - p) package adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot - 23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 tsot - 23, sc70 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot - 23, sc70 adr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot - 23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic-8 adr435 5 0.04 3 0.8 8 soic-8 adr391 2.5 0.16 9 0.12 5 tsot -23 adr395 5 0.10 9 0.12 8 tsot -23 table 10 . suitable adi precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise (v p - p) supply current (a) package op97 2 to 20 2 5 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 0.4 500 msop, soic -8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic -8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic -8 table 11 . suitable adi high sp eed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) vos (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1,500 6,000 soic- 8, sot - 23, msop ad8021 2.5 to 12 490 120 1,000 10,500 soic- 8, msop ad8038 3 to 12 350 425 3,000 750 soic- 8, sc70 -5 ad9631 3 to 6 320 1,300 10,000 7,000 soic-8
ad5428/ad5440/ad5447 rev. b | page 22 of 32 parallel interface data is loaded in to the ad5428/ ad54 40/ ad54 47 in 8- , 10 - , or 12- bit parallel word format . control lines cs and r/ w al low data to be written to or read from the dac register. a write event takes place when cs and r/ w are brought low, data available on the data lines fills the shift register , and the rising edge of cs l atches the data and transfers the latched data - word to the dac register. the dac latches are not transparent ; therefore, a write sequence must consist of a falling and rising edge on cs to ensure that data is lo aded in to the dac register and it s analog equivalent is reflected on the dac output. a read event takes place when r/ w is held high and cs is brought low. d ata is loaded from the dac register , goes back in to the input register , and is out put onto the data line , where it can be read back to the controller for verification or diagnostic purposes. the input and dac registers of these devices are not transparent ; therefore, a falling and rising edge of cs is required to load each data - word. microprocessor inter facing adsp - 21xx - to - ad5428/ad5440/ad5447 interface figure 44 shows the ad5428/ad5440/ad5447 interfaced to the adsp - 21xx series of dsps as a memory - mapped device. a single wait state may b e necessary to interface the ad5428/ ad5440/ad5447 to the adsp - 21xx, depending on the clock speed of the dsp. the wait state can be programmed via the data memory wait state control register of the adsp - 21xx (see the adsp - 21xx family s user manual for deta ils). 04462-055 r/w db0 to db11 ad5428/ ad5440/ ad5447 1 address decoder cs data 0 to data 23 address bus addr 0 to adrr 13 adsp-21xx 1 data bus dms wr 1 additional pins omitted for clarity. figure 44 . adsp21xx -to- ad5428/ad5440/ad5447 interface 8xc51 - to - ad5428/ad5440/ad5447 interface figure 45 shows the interface between the ad5428/ad5440/ ad5447 and the 8xc51 family o f dsps. to facilitate external data memory access, the address latch enable (ale) mode is enabled. the low byte of the address is latched with this output pulse during access to the external memory. ad0 to ad7 are the multiplexed low order addresses and da ta bus , and they require strong internal pull - ups when emitting 1s. during access to external memory, a8 to a15 are the high order address bytes. because these ports are open drained, they also require strong internal pull - ups when emitting 1s. 04462-057 r/w db0 to db11 ad5428/ ad5440/ ad5447 1 address decoder cs ad0 to ad7 address bus a8 to a15 8051 1 data bus wr 1 additional pins omitted for clarity. 8-bit latch ale figure 45 . 8xc51 - to - ad5428/ad5440/ad5447 interface adsp - bf5xx - to - ad5428/ad5440/ad5447 interface figure 46 shows a typical interface between the ad5428/ ad5440/ad5447 and the adsp - bf5xx family of dsps . the asynchronous memory write cycle of the processor drives the digital inputs of the dac. the ams x line is actually four memory select lines. internal addr lines are decoded into ams 3C0 , and then these lines are inserted as chip selects. the rest of the interface is a standard handshaking operation. 04462-056 r/w db0 to db11 ad5428/ ad5440/ ad5447 1 address decoder cs data 0 to data 23 address bus addr 1 to adrr 19 adsp-bf5xx 1 data bus amsx awe 1 additional pins omitted for clarity. figure 46 . adsp - bf5xx - to - ad5428/ad5440/ad5447 interface
ad5428/ad5440/ad5447 rev. b | page 23 o f 32 pcb layout a nd power supply deco upling in a ny circuit where accuracy is import ant, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5428/ ad54 40/ ad54 47 is mounted should be designed so that the analog and digital sections are separate an d confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close as possible to the package, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and low ef fective series inductance (esi), like the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capac itors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast - switching signals should be shielded with digital ground to avoid radiating noise to other par ts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best method , but its use is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to the ground plane , and signal traces are placed on the soldered side. it is good practice to use compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i - to - v amplifier should be located as close as possible to the device. evaluation board for th e ad5447 the evaluation board consists of a n ad5447 d ac and a current - to - voltage amplifier , the ad8065. included on the evaluat ion board is a 10 v reference, the adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd - rom with self -installing pc software to control the dac. the software simply allows the user to write a code to the de vice. power supplies for t he evaluation b oard the board requires 12 v and +5 v supplies. the +12 v v dd and ?12 v v ss are used to power the output amplifier ; the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors.
ad5428/ad5440/ad5447 rev. b | page 24 of 32 04464-037 v dd v ss u3 c7 1.8pf j1 7 4 3 2 6 v? v+ + c11 10f c9 10f c12 0.1f c8 0.1f c3 10f c14 10f c16 10f c18 10f c20 10f c4 0.1f c13 0.1f c15 0.1f c17 0.1f c17 0.1f dgnd c19 0.1f c2 0.1f c1 0.1f c10 0.1f + + c5 10f c6 0.1f + tp1 o/p a v dd v ss u7 c22 1.8pf j6 7 4 3 2 6 v? v+ + c25 10f c23 10f c26 0.1f c24 0.1f + tp4 tp3 tp2 o/p b v dd r fb b v dd +v in v out trim gnd u1 ad5447 u6-a lk1 u2 2 5 3 4 1 v dd 1 a b agnd 23 21 i out b 24 r fb a 3 i out a 2 v ref b v ref a j5 j2 ext ref b ext ref a 22 4 1 17 18 13 14 22 21 20 19 23 24 15 16 5 6 12 11 10 9 8 7 2 1 3 4 b5 b4 oeab leab b0 b1 b2 b3 ceba b7 b6 a2 a3 gnd ceab a7 a6 a5 a4 oeba leba a0 a1 5 6 12 11 10 9 8 7 2 1 3 4 b5 b4 oeab leab b0 b1 b2 b3 ceba b7 b6 a2 a3 gnd ceab a7 a6 a5 a4 oeba leba a0 a1 3 1 2 a0 a1 v cc v cc vcc v cc vcc p1?31 p1?1 p1?8 p1?9 p1?36 p1?14 p1?7 p1?6 p1?5 p1?4 p1?3 p1?2 j4 j3 u5 u4 74abt543 74abt543 17 18 13 14 22 21 11 12 9 10 5 4 7 6 20 19 23 24 15 16 db0 18 db1 17 db7 11 db8 10 db9 9 db10 8 db11 7 cs 19 rw 20 6 db6 12 db5 13 db4 14 db3 15 db2 16 5 dgnd dgnd dgnd db0 db1 db7 db8 db9 db10 db11 cs r/w dac_a/b db6 db5 db4 db3 db2 e y3 y2 y1 y0 u6-b 13 15 14 a0 a1 e y3 y2 y1 y0 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 p2?3 p2?2 p2?1 p2?4 agnd v ss v dd 1 v dd + p2?6 p2?5 + + + v cc figure 47 . schematic of ad5447 evaluation board
ad5428/ad5440/ad5447 rev. b | page 25 of 32 04462-036 figure 48. component-side artwork 04462-038 figure 49. silkscreencomponent-side view (top layer)
ad5428/ad5440/ad5447 rev. b | page 26 of 32 04462-039 figure 50 . solder - side artwork
ad5428/ad5440/ad5447 rev. b | page 27 o f 32 bill of materials table 12. name/ position part desc ription value tolerance ( %) stock code c1 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c2 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c3 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c4 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c5 tantalum c apacitor taj s eries 10 f 10 v 10 fec 197 - 130 c6 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c7 npo c eramic c apacitor 1.8 pf 10 fec 721 - 876 c8 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c9 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c10 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c11 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c12 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c13 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c14 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c15 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c16 tantalum ca pacitor taj s eries 10 f 20 v 10 fec 197 - 427 c17 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c18 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c19 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c20 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197- 427 c21 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c22 npo c eramic c apacitor 1.8 pf 10 fec 721 - 876 c23 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c24 x7r c eramic c apacitor 0.1 f 10 fec 499 - 675 c25 tantalum c apacitor taj s eries 10 f 20 v 10 fec 197 - 427 c26 x7r ce ramic c apacitor 0.1 f 10 fec 499 - 675 cs, db0 to db 11 red t estpoint fec 240 - 345 (pack) j1 to j 6 smb s ocket fec 310 - 682 j2 smb s ocket fec 310 - 682 j3 smb s ocket fec 310 - 682 j4 smb s ocket fec 310 - 682 j5 smb s ocket fec 310 - 682 j6 smb s ocket fec 310 - 682 lk1 3-p in h eader (2 2) fec 511 - 791 and fec 528- 456 p1 36-p in ce ntronics c onnector fec 147 - 753 p2 6-p in t erminal b lock fec 151 - 792 rw red t estpoint fec 240 - 345 (pack) tp1 to tp 4 red t estpoint fec 240 - 345 (pack) u1 ad54 47 a d5447yru u2 adr01 adr01ar u3 ad8065 ad8065ar u4, u5 74abt543 fairchild 74abt543cmtc u6 74139 cd74hct139m u7 ad8065 ad8065ar each corner rubber s tick -o n f eet fec 148 -92 2
ad5428/ad5440/ad5447 rev. b | page 28 of 32 overview of ad54xx d evices table 13. part no. resolution no. dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru - 16, cp -20 10 mhz bw, 17 ns cs p ulse w idth ad5426 8 1 0.25 serial rm- 10 10 mhz bw, 50 mhz s erial ad5428 8 2 0.25 parallel ru -20 10 mhz bw, 17 ns cs p ulse w idth ad5429 8 2 0.25 serial ru -10 10 mhz bw, 50 mhz s erial ad5450 8 1 0.25 serial uj -8 10 mhz bw, 50 mhz s erial ad5432 10 1 0.5 serial rm - 10 10 mhz bw, 50 mhz s erial ad5433 10 1 0.5 parallel ru - 20, cp -20 10 mhz bw, 17 ns cs p ulse w idth ad5439 10 2 0.5 serial ru -16 10 mhz bw, 50 mhz s erial ad5440 10 2 0.5 parallel ru -24 10 mhz bw, 17 ns cs p ulse w idth ad5451 10 1 0.25 serial uj- 8 10 mhz bw, 50 mhz s erial ad5443 12 1 1 serial rm - 10 10 mhz bw, 50 mhz s erial ad5444 12 1 0.5 serial rm -8 10 mhz bw, 50 mhz s erial ad5415 12 2 1 serial ru -24 10 mhz bw, 5 0 mhz s erial ad5405 12 2 1 parallel cp -40 10 mhz bw, 17 ns cs p ulse w idth ad5445 12 2 1 parallel ru - 20, cp -20 10 mhz bw, 17 ns cs p ulse w idth ad5447 12 2 1 parallel ru -24 10 mhz bw, 17 ns cs p ulse wi dth ad5449 12 2 1 serial ru -16 10 mhz bw, 50 mhz s erial ad5452 12 1 0.5 serial uj - 8, rm -8 10 mhz bw, 50 mhz s erial ad5446 14 1 1 serial rm -8 10 mhz bw, 50 mhz s erial ad5453 14 1 2 serial uj - 8, rm -8 10 mhz bw, 50 mhz s erial ad5553 14 1 1 serial rm -8 4 mhz bw, 50 mhz s erial c lock ad5556 14 1 1 parallel ru -28 4 mhz bw, 20 ns wr p ulse w idth ad5555 14 2 1 serial rm -8 4 mhz bw, 50 mhz s erial c lock ad5557 14 2 1 parallel ru -38 4 mhz bw, 20 ns wr p ul se w idth ad5543 16 1 2 serial rm -8 4 mhz bw, 50 mhz s erial c lock ad5546 16 1 2 parallel ru -28 4 mhz bw, 20 ns wr p ulse w idth ad5545 16 2 2 serial ru -16 4 mhz bw, 50 mhz s erial c lock ad5547 16 2 2 parallel ru -38 4 mhz bw, 20 ns wr p ulse w idth 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
ad5428/ad5440/ad5447 rev. b | page 29 of 32 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 51. 20-lead thin shrink outline package [tssop] (ru-20) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 52. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model 1 resolution inl (lsb) temperature rang e package description package option ad5428yru 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5428yru-reel 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5428yru-reel7 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5428yruz 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5428yruz-reel 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5428yruz-reel7 8 0.5 C40 c to +125c 20-lead tssop ru-20 ad5440yru 10 0.5 C40 c to +125c 24-lead tssop ru-24 ad5440yru-reel 10 0.5 C40 c to +125c 24-lead tssop ru-24 ad5440yru-reel7 10 0.5 C40 c to +125c 24-lead tssop ru-24 ad5440yruz 10 0.5 C40 c to +125c 24-lead tssop ru-24 ad5440yruz-reel 12 1 C40 c to +125c 24-lead tssop ru-24 ad5440yruz-reel7 12 1 C40 c to +125c 24-lead tssop ru-24 ad5447yru 12 1 C40 c to +125c 24-lead tssop ru-24 ad5447yru-reel 12 1 C40 c to +125c 24-lead tssop ru-24 ad5447yruz 12 1 C40 c to +125c 24-lead tssop ru-24 AD5447YRUZ-REEL 12 1 C40 c to +125c 24-lead tssop ru-24 AD5447YRUZ-REEL7 12 1 C40 c to +125c 24-lead tssop ru-24 eval-ad5447ebz evaluation kit 1 z = rohs compliant part.
ad5428/ad5440/ad5447 rev. b | page 30 of 32 notes
ad5428/ad5440/ad5447 rev. b | page 31 o f 32 notes
ad5428/ad5440/ad5447 rev. b | page 32 of 32 notes ? 200 4C 2011 a nalog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04462 C0C3/ 11 (b)

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